1. Field of the Invention
The present invention relates to microprocessor technology. More specifically, the present invention pertains to debugging techniques for a microprocessor core.
2. Related Art
Computer systems are extensively used to perform a wide variety of useful operations in modern society. Applications of computer systems can be found in virtually all fields and disciplines, including but not limited to business, industry, scientific research, education and entertainment. For instance, computer systems are used to analyze financial data, to control industrial machinery, to model chemical molecules, to deliver classroom presentations and to generate special effects for movies. Indeed, it has now come to the point where many of these operations have become so computationally intensive that they cannot be efficiently performed without the help of modern computer systems. Strong demand for high performance computing has fueled the rapid development of new and more powerful microprocessors, which are essentially the xe2x80x9cbrainsxe2x80x9d of modern computer systems.
Microprocessor design typically involves an extensive testing phase which serves to validate the design and verify the functionality of the chip. In the case of a stand-alone CPU (central processing unit) chip, a logic analyzer can be used to monitor the chip""s connection pins with one or more companion chips during testing. As such, the general program flow can be observed and debugging can be performed accordingly. However, in the case of microprocessor coreware, such as S-o-C (System-on-Chip), boundary signals of the CPU core are not sent outside of the chip. In particular, these boundary signals are generally not accessible on the circuit board as an LSI terminal. Thus, the conventional testing technique of waveform observation as utilized for testing stand-alone CPU chips and as described above is not practicable in the case of microprocessor coreware testing.
Given these constraints, it is difficult to divide event points during the testing process, and the designer must instead come up with many different types of test programs in order to thoroughly test the CPU core under investigation. As a result, the testing process is very time-consuming.
To alleviate this problem, engineers use the technique of mounting debugging features to the CPU core so as to facilitate the testing process. Under this approach, porting of an application becomes easier. The testing and tuning of the system is also less tedious.
Nevertheless, existing techniques for mounting debugging features to the CPU core is still not ideal. In particular, the download speed of test programs into the CPU core (e.g., via a serial port) is often a limiting factor to the overall efficiency of the testing process. Hence, it would be advantageous to have a method and system wherein microprocessor coreware can be tested in an efficient manner.
Furthermore, it is appreciated that compatibility is essential in developing an testing or debugging interface. More specifically, numerous vendors will offer different components, applications, and development tools for use in a debugging environment. As such, it would be desirable that these different components, applications, and development tools can communicate via the debugging interface such that they can work together seamlessly.
It would be advantageous to provide a method and system wherein a microprocessor core can be tested in an efficient manner. It would also be advantageous to provide a mechanism for high speed download of test programs into a microprocessor core that is to be tested. Furthermore, it would be advantageous for such mechanism to utilize an existing standard which has been adopted in the industry in its implementation such that the mechanism is widely compatible with other applications.
Accordingly, the present invention provides a method and system for debugging a microprocessor core wherein test programs can be download into the core via JTAG pins according to the IEEE 1149.1 standard. In addition, the present invention also provides a set of extensions to the specifications of the N-wire functions, which can then be used in conjunction with the JTAG pins for program download. Importantly, based on the N-wire specification extensions, embodiments of the present invention enables multiple monitor instructions to be executed at the same time. As such, the present invention leverages upon a versatile technology platform for on-chip debugging and delivers a system and method that is not only widely compatible with other applications and development tools provided by numerous third party vendors but is also highly reusable in other chip and board designs. Moreover, embodiments of the present invention provide greatly enhanced test program download speed over existing on-chip debugging implementations. These and other advantages of the present invention not specifically mentioned above will become clear within discussions of the present invention presented herein.
More specifically, in one embodiment, the method of the present invention comprises the step of receiving as input a test program and test data for testing the microprocessor core. The method also comprises the step of storing multiple instructions of the test program into a first register of a debugging module in the microprocessor core. The method further comprises the step of storing a set of data into a second register of the debugging module, wherein the set of data is a subset of the test data. The method also comprises the step of executing those multiple instructions with the set of data. Importantly, those multiple instructions remain in the first register throughout the testing process such that those instructions need only be stored once for all of the test data, even though the test data is processed in separate sets of data. In one embodiment, the present invention includes the above and wherein the debugging module is based on a version of the IEEE 1149.1 standard. In another embodiment, the present invention includes the above and wherein the debugging module supports a version of the N-wire testing standard and extensions thereto.
Embodiments of the present invention include the above and wherein the step of storing multiple instructions of the test program into the first register of the debugging module in the microprocessor core as well as the step of storing the set of data into the second register are repeated until the test data has been completely processed. Additionally, embodiments of the present invention include the above and wherein the multiple instructions and the set of data are stored into the first and second registers, respectively, via JTAG pins coupled to the microprocessor core.